1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices, and more particularly to a method of manufacturing semiconductor devices, which can reduce bit line contact resistance and raise resistance uniformity thereby improving electrical characteristics of devices.
2. Description of the Prior Art
In general, the art currently requires high yield and integration in order to obtain high productive semiconductor devices. Accordingly, resistance within a device is necessarily minimized to accelerate its operation as well as reduce power consumption. This also ensures transistor characteristics for stable transistor operation.
In order to realize the above requirements, a conventional method of manufacturing semiconductor devices activates dopant, which functions to form S/D junctions of a Peri transistor by Rapid Thermal Annealing (RTA).
In the above conventional method, a p+ source/drain junction is in contact with bit lines. In order to reduce the bit line contact resistance, the conventional method first increases the impurity concentration of the p+ source/drain junction and then activates dopant by RTA.
However, the conventional manufacture method for semiconductor devices has the following problems.
The conventional manufacture method requires annealing to be performed at a higher temperature since the contact resistance is increased in proportion to reduction in the size of a semiconductor device. In higher temperature annealing, since thermal activation of dopant is proportional to temperature, resistance is not reduced at a temperature exceeding a proper temperature, but dopant may be deactivated to increase resistance instead.
As a result, high temperature annealing creates residue stress thereby degrading refresh characteristics. Further, RTA disadvantageously lowers resistance uniformity.